1. Technical Field
Embodiments of the invention relate generally to exchanging data in a computer platform. More particularly, certain embodiments relate to the granting of a bus access for a message exchange across multiple data buses of a computer platform.
2. Background Art
Computer architectures may, for various reasons, include multiple different hardware components which implement various respective operating bandwidths—e.g. operating frequencies. Such differences in operating bandwidths may be due to incorporation of legacy hardware components in a computer platform, for example. For efficient use of these different component bandwidths, a set of comparatively low bandwidth components may be separated from a set of comparatively high bandwidth components—e.g. by allocating the sets of components each to different respective data buses.
Such separation of high bandwidth and low bandwidth components from one another may pose problems for message exchanges in the architecture. For example, even though the high bandwidth and the low bandwidth bus are physically different buses, they may reside on the same logical bus segment regulated by a common sideband protocol.
If a sideband communication scheme regulates transactions on both of the two buses, this may impose a transaction coherency requirement. More particularly, logic interfacing the two buses may be required to maintain an order between transactions on the two buses so that their apparent order from some Global Observable Point (GOP) of the platform is the same as the order in which the individual transactions are respectively granted on their respective bus segments. For instance, if some agent A on a high bandwidth bus is granted a posted write transaction to the high bandwidth bus, and sends a sideband indication to an agent B on a low bandwidth bus, indicating that it has finished the transaction, any later transaction from agent B may need to be ordered behind agent A's granted transaction.
Such coherency problems in a multi-bus architecture have been solved by complex arbitration schemes on behalf of at least one of the multiple buses. For example, a first arbitrator of access requests for a first bus may have to be coupled to read information from a second arbitrator of access requests for a second bus. More particularly, the first arbitrator may be required to understand all transactions that have been granted by the second arbitrator, to re-arbitrate transaction requests from a bridge to the second bus and/or to dynamically maintain (e.g. reorder) request ordering between the bridge and components of the first bus. The imposition of such requirements on an arbitration scheme for a given bus has resulted in inefficiency and delay in overall transaction arbitration by such computer architectures, and has limited the scalability of such architectures.